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These bits always reflect the status of the processor, therefore they only have a reset value if the particular reset event affects the processor. For example, a PRESETDBGn event leaves these bits unchanged and a processor reset event such as nSYSPORESET sets DSCR[18] to a 0 and DSCR[1:0] to 10. To use the Debug Status and Control Register, read or write CP14 c1 with: MRC p14, 0, , c0, c1, 0 ; Read Debug Status and Control Register MCR p14, 0, , c0, c1, 0 ; Write Debug Status and Control Register DTR access mode You can use the DTR access mode field to optimize data transfer between a debugger and the processor. The DTR access mode can be one of the following: • Nonblocking. This is the default mode. • Stall. • Fast. In Non-blocking mode, reads from DTRTX and writes to DTRRX and ITR are ignored if the appropriate latched ready flag is not in the ready state. These latched flags are updated on DSCR reads. The following applies: • writes to DTRRX are ignored if DTRRXfull_l is set to b1 • reads from DTRTX are ignored, and return an Unpredictable value, if DTRTXfull_l is set to b0 ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. ID013010 Non-Confidential, Unrestricted Access Debug • writes to ITR are ignored if InstrCompl_l is set to b0 • following a successful write to DTRRX, DTRRXfull and DTRRXfull_l are set to b1 • following a successful read from DTRTX, DTRTXfull and DTRTXfull_l are cleared to b0 • following a successful write to ITR, InstrCompl and InstrCompl_l are cleared to b0. Debuggers accessing these registers must first read DSCR. This has the side-effect of copying DTRRXfull and DTRTXfull to DTRRXfull_l and DTRTXfull_l. The debugger must then: • write to the DTRRX if the DTRRXfull flag was b0 (DTRRXfull_l is b0) • read from the DTRTX if the DTRTXfull flag was b1 (DTRTXfull_l is b1) • write to the ITR if the InstrCompl_l flag was b1. However, debuggers can issue both actions together and later determine from the read DSCR value whether the operations were successful. In Stall mode, the APB accesses to DTRRX, DTRTX, and ITR stall under the following conditions: • writes to DTRRX are stalled until DTRRXfull is cleared • writes to ITR are stalled until InstrCompl is set • reads from DTRTX are stalled until DTRTXfull is set. Fast mode is similar to Stall mode except that in Fast mode, the processor fetches an instruction from the ITR when a DTRRX write or DTRTX read succeeds. In Stall mode and Nonblocking mode, the processor fetches an instruction from the ITR when an ITR write succeeds. 11.4.6 Data Transfer Register The DTR consists of two separate physical registers: • the DTRRX (Read Data Transfer Register) • the DTRTX (Write Data Transfer Register). The register accessed is dependent on the instruction used: • writes, MCR and LDC instructions, access the DTRTX • reads, MRC and STC instructions, access the DTRRX. Note Read and write are used with respect to the processor. For information on the use of these registers with the DTRTXfull flag and DTRRXfull flag, see Debug communications channel on page 11-55. The Data Transfer Register, bits [31:0] contain the data to be transferred. ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. ID013010 Non-Confidential, Unrestricted Access Debug Table 11-11 shows how the bit values correspond with the DTRRX and DTRTX functions. Table 11-11 Data Transfer Register functions Bits Field Function [31:0] Data Reads the Data Transfer Register. This is read-only for the CP14 interface. Note Reads of the DTRRX through the coprocessor interface cause the DTRTXfull flag to be cleared. However, reads of the DTRRX through the APB port do not affect this flag. [31:0] Data Writes the Data Transfer Register. This is write-only for the CP14 interface. Note Writes to the DTRTX through the coprocessor interface cause the DTRRXfull flag to be set. However, writes to the DTRTX through the APB port do not affect this flag. 11.4.7 Watchpoint Fault Address Register The Watchpoint Fault Address Register (WFAR) is a read/write register that holds the address of the instruction that triggers the watchpoint. Figure 11-6 shows the bit arrangement of the Watchpoint Fault Address Register. 31 1 0 Address Reserved Figure 11-6 Watchpoint Fault Address Register format Table 11-12 shows how the bit values correspond with the WFAR functions. Table 11-12 Watchpoint Fault Address Register functions Bits Field Function [31:1] Address This is the address of the watchpointed instruction. When a watchpoint occurs in ARM state, the WFAR contains the address of the instruction causing it plus an offset of 0x8. When a watchpoint occurs in Thumb state, the offset is plus 0x4. [0] Reserved RAZ. 11.4.8 Vector Catch Register The processor supports efficient exception vector catching. The read/write Vector Catch Register controls this, as Figure 11-7 on page 11-20 shows. ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. ID013010 Non-Confidential, Unrestricted ...

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