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The region base address must always align to the region size. The MPU Region Base Address Registers are: • 32-bit read/write registers • accessible in Privileged mode only. Figure 4-34 shows the arrangement of bits in the registers. 31 5 04 Base address Reserved Figure 4-34 MPU Region Base Address Registers format Table 4-31 shows how the bit values correspond with the MPU Region Base Address Register functions. Table 4-31 MPU Region Base Address Registers bit functions Bits Field Function [31:5] Base address Physical base address. Defines the base address of a region. [4:0] Reserved SBZ To access an MPU Region Base Address Register, read or write CP15 with: MRC p15, 0, , c6, c1, 0 ; Read MPU Region Base Address Register MCR p15, 0, , c6, c1, 0 ; Write MPU Region Base Address Register c6, MPU Region Size and Enable Registers The MPU Region Size and Enable Registers: • specify the size of the region specified by the Memory Region Number Register • identify the address ranges that are used for a particular region • enable or disable the region, and its sub-regions, specified by the Memory Region Number Register. The MPU Region Size and Enable Registers are: • 32-bit read/write registers • accessible in Privileged mode only. Figure 4-35 on page 4-51 shows the arrangement of bits in the registers. ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. ID013010 Non-Confidential, Unrestricted Access System Control Coprocessor 31 16 15 8 657 01 Reserved Sub-region disable Region size Reserved Enable Figure 4-35 MPU Region Size and Enable Registers format Table 4-32 shows how the bit values correspond with the MPU Region Size and Enable Registers. Table 4-32 Region Size Register bit functions Bits Field Function [31:16] [15:8] Reserved Sub-region disable Reserved SBZ. Each bit position represents a sub-region, 0-7a. Bit [8] corresponds to sub-region 0 ... Bit [15] corresponds to sub-region 7 The meaning of each bit is: 0 = address range is part of this region 1 = address range is not part of this region. SBZ. [5:1] Region size Defines the region size: b00000 - b00011=Unpredictable b00100 = 32 bytes b00101 = 64 bytes b00110 = 128 bytes b00111 = 256 bytes b01000 = 512 bytes b01001 = 1KB b01100 = 8KB b01101 = 16KB b01110 = 32KB b01111 = 64KB b10000 = 128KB b10001 = 256KB b10010 = 512KB b10011 = 1MB b10110 = 8MB b10111 = 16MB b11000 = 32MB b11001 = 64MB b11010 = 128MB b11011 = 256MB b11100 = 512MB b11101 = 1GB b01010 = 2KB b10100 = 2MB b11110 = 2GB b01011 = 4KB b10101 = 4MB b11111 = 4GB. [0] Enable Enables or disables a memory region: 0 = Memory region disabled. Memory regions are disabled on reset. 1 = Memory region enabled. A memory region must be enabled before it is used. a. Sub-region 0 covers the least significant addresses in the region, while sub-region 7 covers the most significant addresses in the region. For more information, see Subregions on page 7-3. To access an MPU Region Size and Enable Register, read or write CP15 with: MRC p15, 0, , c6, c1, 2 ; Read Data MPU Region Size and Enable Register MCR p15, 0, , c6, c1, 2 ; Write Data MPU Region Size and Enable Register Writing a region size that is outside the range results in Unpredictable behavior. c6, MPU Region Access Control Registers The MPU Region Access Control Registers hold the region attributes and access permissions for the region specified by the Memory Region Number Register. ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. ID013010 Non-Confidential, Unrestricted Access System Control Coprocessor The MPU Region Access Control Registers are: • read/write registers • accessible in Privileged mode only. Figure 4-36 shows the arrangement of bits in the register. 31 1213 811 10 567 3 2 1 0 Reserved XN AP TEX S C B Reserved Figure 4-36 MPU Region Access Control Register format Table 4-33 shows how the bit values correspond with the Region Access Control Register functions. Table 4-33 MPU Region Access Control Register bit functions Bits Field Function [31:13] Reserved SBZ. [12] XN Execute never. Determines if a region of memory is executable: 0 = all instruction fetches enabled 1 = no instruction fetches enabled. [11] -Reserved. [10:8] AP Access permission. Defines the data access permissions. For more information on AP bit values see, Table 4-34. [7:6] Reserved SBZ. [5:3] TEX Type extension. Defines the type extension attributea. [2] S Share. Determines if the memory region is Shared or Non-shared: 0 = Non-shared. 1 = Shared. This bit only applies to Normal, not Device or Strongly Ordered memory. [1] C C bita: [0] B B bita: a. For more information on this region attribute, see Table 7-3 on page 7-9. Table 4-34 shows the AP bit values that determine the permissions for Privileged and User data access. Table 4-34 Access data permission bit encoding AP bit values Privileged permissions User permissions Description b000 No access No access All accesses generate a permission fault b001 Read/write No access Privil...

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