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Guaranteed by statistical correlation. Tested initially and after any design or process changes that may affect these parameters. 9. CMOS output buffer current and power dissipation specified at 50 MHz reference frequency. 10. Applies to REF and FB inputs only. 11. Test measurement levels for the CY7B9910 are TTL levels (1.5V to 1.5V). Test measurement levels for the CY7B9920 are CMOS levels (VCC/2 to VCC/2). Test conditions assume signal transition times of 2ns or less and output loading as shown in the AC Test Loads and Waveforms unless otherwise specified. 12. Except as noted, all CY7B9920–2 and –5 timing parameters are specified to 80 MHz with a 30 pF load. 13. tSKEW is defined as the time between the earliest and the latest output transition among all outputs when all are loaded with 50 pF and terminated with 50. to 2.06V (CY7B9910) or VCC/2 (CY7B9920). 14. tSKEW is defined as the skew between outputs. 15. tDEV is the output-to-output skew between any two outputs on separate devices operating under the same conditions (VCC, ambient temperature, air flow, and so on). 16. tODCV is the deviation of the output from a 50% duty cycle. 17. Specified with outputs loaded with 30 pF for the CY7B99X0–2 and –5 devices and 50 pF for the CY7B99X0–7 devices. Devices are terminated through 50. to 2.06V (CY7B9910) or VCC/2 (CY7B9920). 18. tORISE and tOFALL measured between 0.8V and 2.0V for the CY7B9910 or 0.8VCC and 0.2VCC for the CY7B9920. 19. tLOCK is the time that is required before synchronization is achieved. This specification is valid only after VCC is stable and within normal operating limits. This parameter is measured from the application of a new signal or frequency at REF or FB until tPD is within specified limits. Document Number: 38-07135 Rev. *B Page 6 of 11 [+] Feedback [+] Feedback[+] Feedback CY7B9910 CY7B9920 Switching Characteristics Over the Operating Range[11] (continued) Parameter Description CY7B9910–7 CY7B9920–7 UnitMin Typ Max Min Typ Max fNOM Operating Clock Frequency in MHz FS = LOW[1, 2] 15 30 15 30 MHz FS = MID[1, 2] 25 50 25 50 FS = HIGH1, 2, 3] 40 80 40 80[12] tRPWH REF Pulse Width HIGH 5.0 5.0 ns tRPWL REF Pulse Width LOW 5.0 5.0 ns tSKEW Zero Output Skew (All Outputs)[13, 14] 0.3 0.75 0.3 0.75 ns tDEV Device-to-Device Skew[8, 15] 1.5 1.5 ns tPD Propagation Delay, REF Rise to FB Rise –0.7 0.0 +0.7 –0.7 0.0 +0.7 ns tODCV Output Duty Cycle Variation[16] –1.2 0.0 +1.2 –1.2 0.0 +1.2 ns tORISE Output Rise Time[17, 18] 0.15 1.5 2.5 0.5 3.0 5.0 ns tOFALL Output Fall Time17, 18] 0.15 1.5 2.5 0.5 3.0 5.0 ns tLOCK PLL Lock Time[19] 0.5 0.5 ms tJR Cycle-to-Cycle Output Jitter Peak to Peak[8] 200 200 ps tJR RMS[8] 25 25 ps Document Number: 38-07135 Rev. *B Page 7 of 11 [+] Feedback [+] Feedback[+] Feedback CY7B9910 CY7B9920 AC Timing Diagrams Figure 1. AC Timing Diagrams tODCV tODCV tREF REF FB Q OTHER Q tRPWH tRPWL tPD tSKEW tSKEW tJR Figure 2. Zero Skew and Zero Delay Clock Driver SYSTEM CLOCK FB REF FS Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 TEST Z0 LOAD LOAD LOAD LOAD REF Z0 Z0 Z0 Document Number: 38-07135 Rev. *B Page 8 of 11 [+] Feedback [+] Feedback[+] Feedback CY7B9910 CY7B9920 Operational Mode Descriptions Figure 2 shows the device configured as a zero skew clock Figure 1 shows the CY7B9910/9920 connected in series to buffer. In this mode the 7B9910/9920 is used as the basis for a construct a zero skew clock distribution tree between boards. low skew clock distribution tree. The outputs are aligned and may Cascaded clock buffers accumulates low frequency jitter each drive a terminated transmission line to an independent because of the non-ideal filtering characteristics of the PLL filter. load. The FB input is tied to any output and the operating Do not connect more than two clock buffers in series. frequency range is selected with the FS pin. The low skew specification, coupled with the ability to drive terminated transmission lines (with impedances as low as 50 ohms), enables efficient printed circuit board design. Figure 3. Board-to-Board Clock Distribution SYSTEM CLOCK Z0 FB REF FS TEST REF REF FS FB LOAD LOAD LOAD LOAD LOAD TEST Z0 Z0 Z0 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Document Number: 38-07135 Rev. *B Page 9 of 11 [+] Feedback [+] Feedback[+] Feedback CY7B9910 CY7B9920 Ordering Information Accuracy(ps) Ordering Code Package Type OperatingRange 250 CY7B9910–2SC 24-Pb Small Outline IC Commercial CY7B9910–2SCT 24-Pb Small Outline IC - Tape and Reel Commercial CY7B9920–2SC[20] 24-Pb Small Outline IC Commercial 500 CY7B9910–5SC 24-Pb Small Outline IC Commercial CY7B9910–5SCT 24-Pb Small Outline IC - Tape and Reel Commercial CY7B9910–5SI 24-Pb Small Outline IC Industrial CY7B9910–5SIT 24-Pb Small Outline IC - Tape and Reel Industrial CY7B9920–5SC 24-Pb Small Outline IC Commercial CY7B9920–5SCT 24-Pb Small Outline IC - Tape and Reel Commercial CY7B9920–5SI 24-Pb Small Outline IC Industrial 750 CY7B9910–7SC 24-Pb Small Outline IC Commercial CY7B9910–7SI[20] 24-Pb Small Outline IC Industrial...

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