Stimmen - 2, Durchschnittliche Bewertung: 4.5
(
)
)
|
Anleitung Zusammenfassung
terminated lines ¦ Low operating current ¦ 24-pin SOIC package ¦ Jitter:<200 ps peak to peak, <25 ps RMS Functional Description The CY7B9910 and CY7B9920 Low Skew Clock Buffers offer low skew system clock distribution. These multiple output clock drivers optimize the timing of high performance computer systems. Each of the eight individual drivers can drive terminated transmission lines with impedances as low as 50.. They deliver minimal and specified output skews and full swing logic levels (CY7B9910 TTL or CY7B9920 CMOS). The completely integrated PLL enables “zero delay” capability. External divide capability, combined with the internal PLL, allows distribution of a low frequency clock that is multiplied by virtually any factor at the clock destination. This facility minimizes clock distribution difficulty while allowing maximum system clock speed and flexibility. Block Diagram Description Phase Frequency Detector and Filter The Phase Frequency Detector and Filter blocks accept inputs from the reference frequency (REF) input and the feedback (FB) input and generate correction information to control the frequency of the Voltage Controlled Oscillator (VCO). These blocks, along with the VCO, form a Phase Locked Loop (PLL) that tracks the incoming REF signal. VCO The VCO accepts analog control inputs from the PLL filter block and generates a frequency. The operational range of the VCO is determined by the FS control pin. TEST FB REF VOLTAGE CONTROLLED OSCILLATOR FS Q0 FILTER PHASE FREQ DET Q1 Q2 Q3 Q4 Q5 Q6 Q7 Logic Block Diagram Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Document Number: 38-07135 Rev. *B Revised August 07, 2007 [+] Feedback [+] Feedback[+] Feedback CY7B9910 CY7B9920 Pin Configuration Pin Definitions REF VCCQ FS NC VCCQ VCCN Q0 Q1 GND Q2 Q3 VCCN SOIC Top View 24 GND 2 23 TEST 3 22 NC 4 21 GND 5 20 VCCN 6 7B9910 19 Q7 7 7B9920 18 Q6 8 17 GND 9 16 Q5 10 15 Q4 11 14 VCCN 12 13 FB 1 Signal Name IO Description REF I Reference frequency input.This input supplies the frequency and timing against which all functional variations are measured. FB I PLL feedback input (typically connected to one of the eight outputs). FS[1,2,3] I Three level frequency range select. TEST I Three level select. See TEST MODE. Q[0..7] O Clock outputs. VCCN PWR Power supply for output drivers. VCCQ PWR Power supply for internal circuitry. GND PWR Ground. Test Mode The TEST input is a three level input. In normal system operation, this pin is connected to ground, allowing the CY7B9910 and CY7B9920 to operate as described in Block Diagram Description. For testing purposes, any of the three level inputs can have a removable jumper to ground or be tied LOW through a 100W resistor. This enables an external tester to change the state of these pins. If the TEST input is forced to its MID or HIGH state, the device operates with its internal phase locked loop disconnected and input levels supplied to REF directly control all outputs. Relative output-to-output functions are the same as in normal mode. Notes 1. For all three state inputs, HIGH indicates a connection to VCC, LOW indicates a connection to GND, and MID indicates an open connection. Internal termination circuitry holds an unconnected input to VCC/2. 2. The level to be set on FS is determined by the “normal” operating frequency (fNOM) of the VCO (see Logic Block Diagram). The frequency appearing at the REF and FB inputs are fNOM when the output connected to FB is undivided. The frequency of the REF and FB inputs are fNOM/X when the device is configured for a frequency multiplication by using external division in the feedback path of value X. 3. When the FS pin is selected HIGH, the REF input must not transition upon power up until VCC reached 4.3V. Document Number: 38-07135 Rev. *B Page 2 of 11 [+] Feedback [+] Feedback[+] Feedback CY7B9910 CY7B9920 Maximum Ratings Operating outside these boundaries may affect the performance and life of the device. These user guidelines are not tested. Storage Temperature .................................–65°C to +150°C Ambient Temperature with Power Applied ............................................–55°C to +125°C Supply Voltage to Ground Potential................–0.5V to +7.0V DC Input Voltage ............................................–0.5V to +7.0V Output Current into Outputs (LOW).............................64 mA Static Discharge Voltage............................................ >2001V (MIL-STD-883, Method 3015) Latch Up Current ..................................................... >200 mA Operating Range Ambient Range Temperature VCC Commercial 0°C to +70°C 5V ± 10% Industrial –40°C to +85°C 5V ± 10% Document Number: 38-07135 Rev. *B Page 3 of 11 [+] Feedback [+] Feedback[+] Feedback CY7B9910 CY7B9920 Electrical Characteristics Over the Operating Range Parameter Description Test Conditions CY7B9910 CY7B9920 UnitMin Max Min Max VOH Output HIGH Voltage VCC = Min, IOH = –16 mA ...
Dieses Handbuch ist für folgende Modelle:Time Clocks - CY7B9920 (276.82 kb)