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4) If data is required in less than 52 clock pulses, that part of the data can be gotten by setting the CE pin low after the necessary number of clock pulses have been output. Example: If only the data from “seconds” to “day of the week” is needed: After 28 clock pulses, set the CE pin low in order to get the data from “seconds” to “day of the week.” 5) When performing successive data read operations, a wait (tRCV) is necessary after the CE pin is set low. 6) Note that if an update operation (a one-second carry) occurs during a data read operation, the data that is read will have an error of -1 second. 7) Complete data read operations within tCE (Max.) = 0.9 seconds, as described earlier. 7-2. Data writes 1 2 52 53 54 54+n CLK 0s40 s20 s10 s8s4s2s1 y8 y10 y20 y40 y80 ( FDT ) Seconds Year CE WR DATA 1) When the WR pin is high and the CE pin is high, the RTC enters data input mode. 2) In this mode, data is input, in succession and in synchronization with the rising edge of the CLK signal, to the shift register from the DATA pin, starting from the LSB of the seconds digits. 3) The sub-seconds counter is reset between the falling edge of the first clock pulse and the rising edge of the second clock pulse. In addition, carries to the seconds counter are prohibited at thefalling edge of the first clock pulse. 4) After the last data is input to the shift register at the rising edge of the 52nd clock pulse, the contents of the shift register are transferred to the timer counter. 5) Note that during a data write operation, 52 bits of data must be input. • Correct write-access isn't completed when CE terminal turned into low on a state of less than 52 bits. • If more than 52 bits of data are input, the 53rd and subsequent bits are ignored. (The first 52 bits of data are valid.) 6) Once the CE pin is set low, the prohibition on carries to the seconds counter is lifted. Complete data write operations within tCE (Max.) = 0.9 seconds, as described earlier. 7) If a data read operation is to be performed immediately after a data write operation, a wait (tRCV) is necessary after the CE pin is set low. * Malfunction will result if illegal data is written. Therefore, be certain to write legal data. Page - 7 MQ - 252 - 03 RTC - 4543 SA/SB 7-3. Data writes (Divider Reset) CLK WR DATA s40 s20 s10 s8s4 y8 y10 y20 y40 CE y80 1 522 N Seconds s1 Divider reset Pulse s2 Timer,counter N seconds N seconds 0 seconds Carry stop Pulse After the counter is reset, carries to the seconds digit are halted.After the data write operation, the prohibition on carries to the seconds counter is lifted by setting the CE pin low. Complete data write operations within tCE (Max.) = 0.9 seconds, as described earlier. 7-4. FOUT output and 1 Hz carries CLK WR CE 1Hz FOUT CLK tCES t1.0 s 0 -7.8 ms 15.6 ms 15.6 ms During a data write operation, because a reset is applied to the Devider counter (from the 128 Hz level to the 1 Hz level) after the CE pin goes high during the time between the falling edge of the first clock cycle and the rising edge of the second clock cycle, the length of the first 1 Hz cycle after the data write operation is 1.0 s +0/ .7.8ms +tCES+tCLK. Subsequent cycles are output at 1.0-second intervals. The 1-Hz signal that is output on FOUT is the internal 1-Hz signal with a 15.6-ms shift applied. Page - 8 MQ - 252 - 03 RTC - 4543 SA/SB 8. Examples of External Circuits • Example 1. When used as an RTC + clock source RTC 4543 VDD CE GND 0.1 .F FOUT FSEL WR DATA CLK FOE VDD VDD Power supplyDetection circuit Power supplySwitching circuit *1 *2 *1: FOUT output frequency setting (High: 1 Hz; low: 32.768 kHz) *2: Prohibits FOUT output during back up, reducing current consumption. • Example 2. When used as a clock source (oscillator) RTC-4543 VDD CE VDD VDD WR DATA CLK VDD 0.1 .F FOUT FSEL FOE .1 GND Page - 9 MQ - 252 - 03 RTC - 4543 SA/SB 9. External Dimensions RTC - 4543 SA ( SOP-14pin ) 10.1 ± 0.2 5.0 7.4 ± 0.2 1.27 1.2 0.05 Min. 3.2 ± 0.1 0.35 0.6 0.15 0 - 10° . The cylinder of the crystal oscillator can be seen in this area ( front ), but it has no affect on the performance of the device. RTC - 4543 SB ( SOP-18pin ) 7.8 ± 0.2 5.4 11.4 ± 0.2 1.27 0.4 1.8 2.0 0.12 0.1 Max. 0 Min. 0.15 0.6 ± 0.2 0 - 10 10. Layout of Package Markings RTC - 4543 SA ( SOP-14pin ) R4543 E 1234A Model Manufacturing Lot B Frequencytorerance RTC - 4543 SB ( SOP-18pin ) R4543 E 1234A Model ManufacturingLot B Frequencytolerance Note : The markings and their positions as pictured above are only approximations. These illustrations do not define the details of the style, size, and position of the characters marked on the packages. Page - 10 MQ - 252 - 03 RTC - 4543 SA/SB 11. Reference Data (1) Example of Frequency-Temperature Characteristics .T = +25 °C Typ. . = -0.035 . 10-6/ °C 2 Typ. Temperature [°C] -150 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 +10 -50 -40 -30 -20 -10 0 +10 +20 +30 +40 +50 +60 +70 +80 +90+100 Frequency fT. . 10-6 Determining the f...

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