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Anleitung Epson, modell RTC-72423

Hersteller: Epson
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When the HOLD bits is 1 and the BUSY bit is 0, read and write are enabled. When the HOLD bit is 1, any incrementation in the count is held within the RTC. The held incrementation is automatically compensated for when the HOLD bit becomes 0. (Second and subsequent incrementations are ignored.) Therefore, if the HOLD bit is at 1 for two or more seconds in succession, the time will be slightly slow (delay). Make sure that any access to the S1 to W registers is completed within one second, then clear the HOLD bit to 0. The status of the BUSY bit remains as set while the HOLD bit is at 1. If the HOLD bit is not cleared temporarily to 0, the BUSY bit will not indicate any change within the RTC of the BUSY status. Therefore, when checking the status of the BUSY bit, write 0 to the HOLD bit each time the BUSY bit is read, to update the status of the BUSY bit. If the CS1 pin goes low while the HOLD bit is 1, the HOLD bit is automatically cleared to 0. There is no need to use the HOLD bit when accessing the control registers (CD, CE, and CF). (2) BUSY bit (D1) The BUSY bit indicates whether or not the digits from the seconds digit onward are being incremented, and is used when accessing the S1 to W registers. For details, see "Read/write of S1 to W registers". There is no need to check the BUSY bit when accessing the control registers (CD, CE, and CF). BUSY bit Significance of the BUSY bit Condition Remarks 0 Access enable HOLD=1 The RTC is not counting 1 Access disabled The count has been incremented in the RTC (190 .s Max.) 1 BUSY is always 1 HOLD=0 The count cannot be checked The status of the BUSY bit remains as set while the HOLD bit is at 1. If the HOLD bit is not cleared temporarily to 0, the BUSY bit will not indicate any change within the RTC of the BUSY status. Therefore, when checking the status of the BUSY bit, write 0 to the HOLD bit each time the BUSY bit is read, to update the status of the BUSY bit. The BUSY bit is a read-only bit, so any attempt to write 1 or 0 to it is ignored. (3) IRQ FLAG bit (D2) The IRQ FLAG bit is an internal status bit that corresponds to the status of the STD.P pin output, to indicate whether or not an interrupt request has been issued to the CPU. When the STD.P pin output is low, the IRQ FLAG bit is 1; when the STD.P pin output is open-circuit, the IRQ FLAG bit is 0. When writing data to the CD register, keep the IRQ FLAG bit at 1, except when deliberately writing 0 to it. Writing 0 to the IRQ FLAG bit cancels its status if it had become 1 at that instant or just before. i. Interrupt processing (interrupt status monitor function) Since the IRQ FLAG bit indicates that an interrupt request has been generated to the CPU, it is in synchronization with the status of the STD.P pin output. In other words, the status of the STD.P pin output can be monitored by monitoring the IRQ FLAG bit. In fixed-period pulse output mode, the relationship between the IRQ FLAG bit and the STD.P pin output is as follows: STD.P pin output IRQ FLAG bit Low 1 Open(for open-drain output) 0 The timing of the IRQ FLAG bit and the STD.P pin output in fixed-period pulse output mode is as follows: *STD.P pin output IRQ FLAG bit 0 1 0 Approx. 1.95 ms 7.8125 ms The output levels of the STD.P pin are low (down) and open circuit (up). ii. STD.P pin output reset function The STD.P pin output can be reset after an interrupt is generated by writing 0 to the IRQ FLAG bit. The relationships of this operation are shown below. Note that writing 1 to this bit is possible, but it has no effect. IRQ FLAG bit STD.P pin output 1 Low 0 Open(for open-drain output) Page - 10 MQ - 162 - 03 RTC - 72421 / 72423 *STD.P pin output IRQ FLAG bit 0 1 0 1 Interrupt generation (in synchronization with count incrementation) Writing of 0 IRQ FLAG bit. The output levels of the STD.P pin are low (down) and open circuit (up). Note: If the STD.P pin output remains low as set, subsequently generated interrupts are ignored. In order to prevent interrupts from being overlooked, write 0 to the IRQ FLAG bit before the next interrupt is generated, to return the STD.P pin to high. iii. Initial setting of IRQ FLAG bit If the fixed-period interrupt mode is not used, set the IRQ FLAG bit to 1. If the fixed-period interrupt mode is used, set the IRQ FLAG bit to 0. (4) 30-second ADJ bit (D3) The 30-seconds ADJ bit provides a 30-seconds correction (by which term is meant a rounding to the nearest whole minute) when 1 is written to it. The 30-seconds correction takes a maximum of 76.3 .s to perform, and after the correction the 30seconds ADJ bit is automatically returned to 0. This operation also clears the sub-second bits of the internal counter down to the 1/256-seconds counter. During the 30-seconds correction, access to the counter registers at addresses 0 to C is inhibited, so monitor the 30-seconds ADJ bit to check that this bit has returned to 0, before starting subsequent processing. If no access is made to the RTC for 76.3 .s or more after 1 is wri...