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Anleitung Zusammenfassung
The Choice: 3T, 2T, 4T, Reserved. u RAS TO CAS DELAY This item defines SDRAM ACT to Read/Write command period. The choice: 3T, 2T, 4T, Reserved. u DRAM BACKGROUND COMMAND This item is lead-off time control for DRAM background command. When select 'Delay 1T', background commands are issued 1 clock behind memory address (MA) been issued. When select 'Normal', background command and MA are issued at the same time. The choice: Delay 1T or Normal. 7-118 APOLLO 120/150 III User Manual version 2305 u LD-OFF DRAM RD/WR CYCLES The item is lead-off time control for DRAM Read/Write Cycles. When select 'Delay 1T', memory read/write command is issued 1 clock behind memory address (MA) been issued. When select 'Normal', read/write command amd MA are issued at the same time. The choice: Delay 1T or Normal. u WRITE RECOVERY TIME This item defines the Data-in to PRE command period. The choice: 1T or 2T u VCM REF TO ACT/REF DELAY This item defines VCM REF to REF/ACT command period. The choice: 10T, or 9T. u VCM ACCT TO ACT/REF DELAY This item defines VCM ACT to ACT/REF command period. The choice: 10T, 9T, 8T or Reserved. u EARLY CKE DELAY 1T CNTRL When this item is enabled, CKE is driven out from flip-flop. It is used when system operates under low frequency and CKE delay adjustment method defined in the 'Early CKE Delay Adjustment' which can not meet setup time and hold time requirement. The choice: Normal, Delay 1T. u Early CKE Delay Adjust This item controls the timing for CKE. Various delay options are provided to ensure that CKE can meet SDRAM setup time and hold time specification when CKE is driven out. The Choice: 1ns, 2ns, 3ns, 4ns, 5ns, 6ns, 7ns, 8ns. u MEM COMMAND OUTPUT TIME This item is to control the timing to drive memory command onto memory bus. The choice: Normal, Delay 1T. APOLLO 120/150 III 7-119 User Manual version 2305 u SDRAM/VCM CAS LATENCY When synchronous DRAM is installed, the number of clock cycles of CAS latency depends on the DRAM timing. The Choice: 2, 3 or SPD u SDRCLK CONTROL This item controls the phase of SDRCLK that lags behind SDCLK. The choice: Enabled or Disabled. u SDWCLK CONTROL CS#/CKE This item controls the phase of SDWCLK used for chip set select signals pin that lags ahead SDCLK. The choice: Enabled or Disabled. u SDWCLK CONTROL MA/SRAS This item controls the phase of SDWCLK used for MA/ SRAS signals that lags ahead SDCLK. The choice: +5.0ns~-2.5ns (Default 0.0ns) u SDWCLK CONTROL DQM/MD This item controls the phase of SDWCLK used for DQM/MD signals that lags ahead SDCLK. The choice: +5.0ns~-2.5ns (Default 0.0ns) u EGMRCLK CONTROL This item controls the phase of EGMRCLK that lags behind SDCLK. The choice: -1.0ns~+6.5ns (Default 0.0ns) u EGMWCLK CONTROL This item controls the phase of EGMWCLK that lags ahead SDCLK. The choice: +5.0ns~-2.5ns (Default 0.0ns) 7-120 APOLLO 120/150 III User Manual version 2305 u SYSTEM BIOS CACHEABLE Selecting Enabled allows caching of the system BIOS ROM at F0000h-FFFFFh, resulting in better system performance. However, if any program writes to this memory area, a system error may result. The choice: Enabled or Disabled. u VIDEO RAM CACHEABLE Select Enabled allows caching of the video RAM , resulting in better system performance. However, if any program writes to this memory area, a system error may result. The choice: Enabled or Disabled. u MEMORY HOLE AT 15M-16M You can reserve this area of system memory for ISA adapter ROM. When this area is reserved, it cannot be cached. The user information of peripherals that need to use this area of system memory usually discusses their memory requirements. The choice: Enabled or Disabled. u AGP APERTURE SIZE Select the size of Accelerated Graphics Port (AGP) aperture. The aperture is a portion of the PCI memory address range dedicated for graphics memory address space. Host cycles that hit the aperture range are forwarded to the AGP without any translation. The Choice: 4M, 8M, 16M, 32M, 64M, 128M, 256M u GRAPHIC WINDOW WR COMBIN Use this item to enable or disable CPU support for WR Combin. The choice: Enabled or Disabled. APOLLO 120/150 III 7-121 User Manual version 2305 u CONCURRENT FUNCTION (MEM) This item is CPU & PCI Masters Concurrently Access Memory Function. Select enabled allows CPU access memory cycles and PCI masters access memory cycles concurrently issued onto host bus and PCI bus, respectively, and then the memory access cycles will be rearranged by SiS630 to memory sequentially. The choice: Enabled or Disabled. u CONCURRENT FUNCTION (PCI) This item is CPU & PCI Masters Concurrently Access PCI Bus Function. Select enabled allows CPU access PCI bus cycle and PCI masters access memory cycles concurrently issued onto host bus and PCI bus, respectively. The choice: Enabled or Disabled. u CPU PIPELINE CONTROL When enabled this item, only one pending cycle is allowed at one time. When disabled, there might be more than two pending cycles at one time depends on the CPU behavior. The choice: Enabled or Disa...
Dieses Handbuch ist für folgende Modelle:PC Notebooks - 150 III (2.04 mb)