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Anleitung Zusammenfassung
Aggregate throughput of up to 12 Gbits/second ¦ Second-generation HOTLink® technology ¦ Compliant to multiple standards . SMPTE-292M, SMPTE-259M, DVB-ASI, Fibre Channel, ESCON, and Gigabit Ethernet (IEEE802.3z) . 10 bit uncoded data or 8B/10B coded data ¦ Truly independent channels . Each channel is able to: • Perform reclocker function • Operate at a different signaling rate • Transport a different data format ¦ Internal phase-locked loops (PLLs) with no external PLL components ¦ Selectable differential PECL compatible serial inputs per channel . Internal DC restoration ¦ Redundant differential PECL compatible serial outputs per channel . No external bias resistors required . Signaling rate controlled edge rates . Source matched for 50. transmission lines ¦ MultiFrame™ Receive Framer provides alignment options . Comma or full K28.5 detect . Single or multibyte Framer for byte alignment . Low latency option ¦ Selectable input and output clocking options ¦ Synchronous LVTTL parallel interface ¦ JTAG boundary scan ¦ Built In Self Test (BIST) for at-speed link testing ¦ Link quality indicator by channel . Analog signal detect . Digital signal detect ¦ Low power 3W at 3.3V typical ¦ Single 3.3V supply ¦ 256 ball thermally enhanced BGA ¦ 0.25. BiCMOS technology ¦ JTAG device ID ‘0C811069’x Functional Description The CYV15G0404DXB Independent Clock Quad HOTLink II™ Transceiver is a point-to-point or point-to-multipoint communications building block enabling the transfer of data over a variety of high speed serial links including SMPTE 292, SMPTE 259, and DVB-ASI video applications. The signaling rate can be anywhere in the range of 195 to 1500 MBaud for each serial link. Each channel operates independently with its own reference clock allowing different rates. Each transmit channel accepts parallel characters in an input register, encodes each character for transport, and then converts it to serial data. Each receive channel accepts serial data and converts it to parallel data, decodes the data into characters, and presents these characters to an output register. The received serial data can also be reclocked and retransmitted through the serial outputs. Figure 1 illustrates typical connections between independent video coprocessors and corresponding CYV15G0404DXB chips. Figure 1. HOTLink II™ System Connections Video Coprocessor Serial Links 10 10 10 10 10 10 10 10 Video Coprocessor 10 10 10 10 10 10 10 10 Serial Links Serial Links Serial Links Cable Connections Independent CYV15G0404DXB Independent Reclocker Reclocker Channel CYV15G0404DXB Channel Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Document #: 38-02097 Rev. *B Revised December 14, 2007 [+] Feedback [+] Feedback[+] Feedback CYV15G0404DXB The CYV15G0404DXB satisfies the SMPTE-259M and SMPTE-292M compliance according to SMPTE EG34-1999 Pathological Test Requirements. As a second generation HOTLink device, the CYV15G0404DXB extends the HOTLink family with enhanced levels of integration and faster data rates, while maintaining serial link compatibility (data, command, and BIST) with other HOTLink devices. The transmit (TX) section of the CYV15G0404DXB Quad HOTLink II consists of four independent byte-wide channels. Each channel accepts either 8-bit data characters or preencoded 10-bit transmission characters. Data characters may be passed from the transmit input register to an integrated 8B/10B Encoder to improve their serial transmission characteristics. These encoded characters are then serialized and output from dual Positive ECL (PECL) compatible differential transmission-line drivers at a bit rate of either 10 or 20 times the input reference clock for that channel. The receive (RX) section of the CYV15G0404DXB Quad HOTLink II consists of four independent byte wide channels. Each channel accepts a serial bit stream from one of two PECL-compatible differential line receivers, and using a completely integrated Clock and Data Recovery PLL, recovers the timing information necessary for data reconstruction. Each recovered bit stream is deserialized and framed into characters, 8B/10B decoded, and checked for transmission errors. Recovered decoded characters are then written to an internal elasticity buffer, and presented to the destination host system. The integrated 8B/10B encoder or decoder may be bypassed for systems that present externally encoded or scrambled data at the parallel interface. The parallel IO interface may be configured for numerous forms of clocking to provide the highest flexibility in system architecture. In addition to clocking the transmit path with a local reference clock, the receive interface may also be configured to present data relative to a recovered clock or to a local reference clock. Each transmit and receive channel contains an independent BIST pattern generator and checker. This BIST hardware allows at speed testing of the high speed serial data paths in each transmit and r...