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Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Adobe Systems PIN CONFIGURATION—ADSST-218X Adobe Systems 03738-0-009543276981D19D18D17D16IRQE+PF4IRQL0+PF5GNDIRQL1+PF6DT0TFS0SCLK0VDDEXTDT1/ FOTFS1/IRQ1DR1/ FIGNDSCLK1ERESETRESETD15D14D13D12GNDD11D10D9VDDEXTGNDD8D7/IWRD6/IRDD5/IALD4/ISGNDVDDINTD3/IACKD2/IAD15D1/IAD14D0/IAD13BGEBGBREBRA4/IAD3A5/IAD4A6/IAD5A7/IAD6A8/IAD7A9/IAD8A10/IAD9A11/IAD10A12/IAD11A13/IAD12GNDGNDCLKINXTALCLKOUTGNDVDDINTVDDEXTWRRDBMSDMSPMSIOMSCMS71727374697067686566756061626358595657545564525351100999897969594939291908988878685848382818079787776PIN 1IDENTIFIERTOP VIEW(Not to Scale) 2627282930313233343536373839404142434445464748495011101615141318172019222112242325ADSST-218xIRQ2+ PF7RFS0DR0EMSEEELOUTECLKELINEINTA3/IAD2A2/IAD1A1/IAD0A0PWDACKBGHFL0FL1FL2D23D22D21D20GNDPF1 [MODE B] GNDPWDVDDEXTPF0 [ MODE A] PF2 [MODE C] PF3 [ MODE D] RFS1/IRQ0 Figure 5. Pin Configuration for ADSST-218x in 100-Lead LQFP GENERAL DESCRIPTION OF THE ADSST-73360LAR ADC The ADSST-73360LAR is a 6-channel input analog front end processor for general-purpose applications, including industrial power metering or multichannel analog inputs. It features six 16-bit A/D conversion channels, each of which provides 76 dB signal-to-noise ratio over a dc to 4 kHz signal bandwidth. Each channel also features an input programmable gain amplifier (PGA) with gain settings in eight stages from 0 dB to 38 dB. The ADSST-73360LAR is particularly suitable for industrial power metering as each channel samples synchronously, ensur- ing that there is no (phase) delay between the conversions. The ADSST-73360LAR also features low group delay conversions on all channels. An on-chip reference voltage is included with a nominal value of 1.2 V. The ADSST-73360LAR is available in a 28-lead SOIC package. Adobe Systems VINP1SDISDIFSSCLKRESETMCLKSESDOSDOFSVINN1VINP2VINN2VINP3VINN3VINP4REFCAPREFOUTVINN4VINP5VINN5VINP6VINN6SIGNALCONDITIONINGREFERENCEDECIMATOR0/38DBPGA0/38DBPGA0/38DBPGA0/38DBPGA0/38DBPGA0/38DBPGADECIMATORDECIMATORDECIMATORDECIMATORDECIMATORSIGNALCONDITIONINGSIGNALCONDITIONINGSIGNALCONDITIONINGSIGNALCONDITIONINGSIGNALCONDITIONINGSIGNAL.-.CONDITIONINGADSST-73360LARSERIALI/OPORTSIGNAL.-.CONDITIONINGSIGNAL.-.CONDITIONINGSIGNAL.-.CONDITIONINGSIGNAL.-.CONDITIONINGSIGNAL.-.CONDITIONING03738-0-004 Figure 6. ADSST-73360LAR Functional Block Diagram SPECIFICATIONS—ADSST-73360LAR (AVDD = 2.7 V to 3.6 V, DVDD = 2.7 V to 3.6 V, DGND = AGND = 0 V, fMCLK = 16.384 MHz, fSCLK = 8.192 MHz, fS = 8 kHz, TA = TMIN to TMAX1, unless otherwise noted.) Table 6. Parameter Min Typ Max Unit Test Conditions REFERENCE REFCAP Absolute Voltage, VREFCAP 1.08 1.2 1.32 V REFCAP TC 50 ppm/°C 0.1 .F Capacitor Required from REFCAP to AGND2 REFOUT Typical Output Impedance 130 . Absolute Voltage, VREFOUT 1.08 1.2 1.32 V Unloaded Minimum Load Resistance 1 k. Maximum Load Capacitance 100 pF ADC SPECIFICATIONS Maximum Input Range at VIN 2, 3 1.578 V p-p Measured Differentially –2.85 dBm Nominal Reference Level at VIN (0 dBm0) 1.0954 V p-p Measured Differentially –6.02 dBm Absolute Gain PGA = 0 dB –1.3 +0.6 dB 1.0 kHz PGA = 38 dB –0.8 +0.8 dB 1.0 kHz Signal to (Noise + Distortion) PGA = 0 dB 76 dB 0 Hz to 4 kHz; fS = 8 kHz PGA = 0 dB 71 76 dB 0 Hz to 2 kHz; fS = 8 kHz fIN = 60 kHz PGA = 38 dB 58 dB 0 Hz to 4 kHz; fS = 64 kHz Total Harmonic Distortion PGA = 0 dB –80 –71 dB 0 Hz to 2 kHz; fS = 8 kHz; fIN = 60 kHz PGA = 38 dB –64 dB 0 Hz to 2 kHz; fS = 64 kHz; fIN = 60 kHz Intermodulation Distortion –78 dB PGA = 0 dB Idle Channel Noise –68 dB PGA = 0 dB, fS = 64 kHz; SCLK = 16 MHz Crosstalk ADC-to-ADC –95 dB ADC1 at Idle; ADC2 to ADC6 Input Signal: 60 Hz DC Offset –30 +30 mV PGA = 0 dB Power Supply Rejection –55 dB Input Signal Level at AVDD and DVDD Pins 1.0 kHz, 100 mV p-p Sine Wave Group Delay4, 5 25 .s 64 kHz Output Sample Rate 50 .s 32 kHz Output Sample Rate 95 .s 16 kHz Output Sample Rate 190 .s 8 kHz Output Sample Rate Input Resistance at VIN2, 4 25 k.6 DMCLK = 16.384 MHz Phase Mismatch 0.15 Degrees fIN = 1 kHz 0.01 Degrees fIN = 60 Hz FREQUENCY RESPONSE (ADC)7 Typical Output Frequency (Normalized to fS) 0 0 dB 0.03125 –0.1 dB 0.0625 –0.25 dB 0.125 –0.6 dB 0.1875 –1.4 dB 0.25 –2.8 dB 0.3125 –4.5 dB 0.375 –7.0 dB 0.4375 –9.5 dB > 0.5 < –12.5 dB LOGIC INPUTS VINH, Input High Voltage VDD – 0.8 VDD V VINL, Input Low Voltage 0 0.8 V IIH, Input Current 10 .A CIN, Input Capacitance 10 pF LOGIC OUTPUT VOH, Output High Voltage VDD – 0.4 VDD V |IOUT| . 100 .A VOL, Output Low Voltage 0 0.4 V |IOUT| . 100 .A Three-State Leakage Current –10 +10 .A POWER SUPPLIES AVDD1, AVDD2 2.7 3.6 V DVDD 2.7 3.6 V IDD8 See Table 7 1Operating temperature range is as follows: –40°C to +85°C. Therefore, TMIN = –40°C and TMAX = +85°C. 2Test conditions: Input PGA set for 0 dB gain (unless otherwise noted). 3At input to sigma-delta modulator of ADC. 4Guaranteed by design. 5Overall group delay will be affected by the sample rate and the external digital ...

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