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Removes ordering restrictions for out-bound read response data with respect to in-bound write data. Setting this bit also causes the GLPCI to clear the SEND_RESPONSE flag for in-bound GLIU request packets. This bit should be cleared for normal operation. 7 BZ Bizarro Flag. BIZARRO flag configuration to use on in-bound I/O reads and writes. 6 NI No Invalidate Flag. Force the INVALIDATE flag to be cleared for all in-bound writes. 5 ISO In-Bound Strong Ordering. Disables the ability of in-bound reads to coherently pass posted in-bound writes. When set to 1, a PCI read request received by the host bridge target is not forwarded to GLIU until all posted write data has been flushed to memory. This bit should be cleared for normal operation. 4 OWC Out-Bound Write Combining. Enables concatenation of out-bound write bursts into a larger PCI burst. Setting this bit does NOT add any additional latency to out-bound writes. 3 IWC In-Bound Write Combining. Enables combining of different in-bound PCI write transactions into a single GLIU host write transaction. When cleared to 0, PCI write data received from the host bridge target is not held in the posted write buffer; a GLIU transaction is generated immediately. 2 PCD In-Bound PCI Configuration Disable. Disables the handling of in-bound PCI configuration cycles. When set to 1, PCI configuration cycles are not accepted by this PCI interface. After reset, the GLPCI module accepts in-bound PCI configuration cycles to provide a means of generating MSR transactions onto the internal GLIU. For normal operation this capability should be disabled. 1 IE I/O Enable. Enable handling of in-bound I/O transactions from PCI. When set to 1, the PCI interface accepts all in-bound I/O transactions from PCI. This mode is only intended for design verification purposes. When cleared to 0, no in-bound I/O transactions are accepted. 0 ME Memory Enable. Enable handling of in-bound memory access transaction from PCI. When cleared to 0 the PCI interface does not accept any in-bound memory transactions from the PCI bus. When set to 1, the PCI interface accepts in-bound memory transactions for those address ranges defined in the region configuration registers. 6.16.2.2 GLPCI Arbiter Control (GLPCI_ARB) MSR Address 50002011h Type R/W Reset Value 00000000_00000000h GLPCI_ARB Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 CR R2 R1 R0 CH H2 H1 H0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RSVD COVOV2OV1OV0RSVDMSK2MSK1MSK0RSVD CPREPRE2PRE1PRE0BM1BM0RSVD EABMDPARK AMD Geode™ LX Processors Data Book 33234H GeodeLink™ PCI Bridge Register Descriptions GLPCI_ARB Bit Definitions Bit Name Description 63:60 CR CPU Repeat. Controls the number of consecutive grants given to the CPU before rotating to the next requestor. This is only valid if there is a non-zero value for the CPU Hold- Grant control (CH, bits [47:44]). This may be overidden by either OV2, OV1 or OV0 (bits [22:20]). It is also ignored if the CPRE (bit 11) is cleared. 59:56 R2 Request Repeat 2. Controls the number of consecutive grants given to PCI requestor 2 before rotating to the next requestor. This is only valid if there is a non-zero value for the Request Hold-Grant2 control (H2, bits [43:40]). This may be overidden by either COV, OV1, or OV0 (bits [23,21,20]. It is also ignored if the ARB.PRE2 bit is cleared. 55:52 R1 Request Repeat 1. Controls the number of consecutive grants given to PCI requestor 1 before rotating to the next requestor. This is only valid if there is a non-zero value for the Request Hold-Grant1 control (H1, bits [39:36]). This may be overidden by either COV, OV2, or OV1 (bits [23,22,21]. It is also ignored if the PRE1 (bit 9) is cleared. 51:48 R0 Request Repeat 0. Controls the number of consecutive grants given to PCI requestor 0 before rotating to the next requestor. This is only valid if there is a non-zero value for the Request Hold-Grant0 control (H0, bits [35:32]). This may be overidden by either the ARB.COV, ARB.OV2 or ARB.OV1 controls. It is also ignored if PRE0 (bit 8) is cleared. 47:44 CH CPU Hold-Grant Controls. Controls the number of PCI clock edges that the PCI bus must be idle after a CPU transaction before arbitration continues. This is only valid if there is a non-zero value for the CPU Repeat field (CR, bits [63:60]). This may be overidden by either OV2, OV1, or OV0 (bits [22,21,20]). It is also ignored if CPRE (bit 11) is cleared. 43:40 H2 Request Hold-Grant 2. Controls the number of PCI clock edges that the PCI bus must be idle after a requestor 2 transaction before arbitration continues. This is only valid if there is a non-zero value for the Request Repeat 2 field (R2, bits [59:56]). This may be overidden by either COV, OV1, or OV0 (bits [23,21,20]). It is also ignored if PRE2 (bit 10) is cleared. 39:36 H1 Request Hold-Grant 1. Controls the number of PCI clock edges that the PCI bus must be idle aft...

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