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Anleitung Zusammenfassung
When jumper FLT0 is installed, filtering is introduced for input bit 0, FLT1 for bit 1, and so on. The tables below describe filtering for Port 0. Ports 1 and 2 follow the same pattern with Port 1 having FLT16-31 (Bits 16-31) and Port 2 having FLT32-47 (Bits 32-47). Filtering provides a slower response for DC signals as described previously and must be used when AC inputs are applied. JUMPER SELECTION Bit Filtered JUMPER SELECTION Bit Filtered FLT-0 FLT-1 FLT-2 ... Bit 0 Bit 1 Bit 2 ... FLT-8 FLT-9 FLT-10 ... Bit 8 Bit 9 Bit 10 ... Chapter 4: Address Selection This card uses I/O addresses offset from the base address assigned by the PCI bus. The address spaces are defined in the Programming section of this manual. PCI architecture is Plug-and-Play. This means that the BIOS or Operating System determines the resources assigned to PCI cards rather than the user selecting these resources with switches or jumpers. As a result, you cannot set or change the card’s base address or IRQ level. You can only determine what the system has assigned. To determine the base address that has been assigned, run the PCIFind utility program. This utility will display a list of all the cards detected on the PCI bus, the addresses assigned to each function on each of the cards, and the respective IRQs. Alternatively, Windows systems can be queried to determine which resources were assigned. In these operating systems, you can use either PCIFind, or the Device Manager utility from the System Properties applet of the control panel. The card is installed in the Data Acquisition class of the Device Manager list. Selecting the card, clicking Properties, and then selecting the Resources Tab will display a list of the resources allocated to the card. The PCI bus supports 64K of I/O address space, so your card’s addresses may be located anywhere in the 0000h to FFFFh range. The card occupies eight consecutive 8 bit registers in the I/O address space. PCIFind uses the Vendor ID and Device ID to search for your card, then reads the base address and IRQ. If you want to determine the base address and IRQ without using PCIFind, use the following information: The Vendor ID code is 494F (ASCII for “I/O”) The Device ID code for the card is 0920 An example of how to locate PCI card resources is provided in the PCI/SOURCE directory, under your installation directory. This code runs in DOC, and uses the PCI defined interrupt BIOS calls to query the PCI bus for card-specific information. You will need the Device ID and Vendor ID listed above to use this code. Chapter 5: Programming The base address is assigned by the computer system during installation and will fall on an eight byte boundary. The card’s read and write functions are as follows: Address Read Write Base Address + 0 Port 0 Low Byte N/A Base Address + 1 Port 0 High Byte N/A Base Address + 2 Port 1 Low Byte N/A Base Address + 3 N/A N/A Base Address + 4 Port 1 High Byte N/A Base Address + 5 Port 2 Low Byte N/A Base Address + 6 Port 2 High Byte N/A Base Address + 7 IRQ Status Register/IRQ Clear IRQ Enable/Disable Note: Base + 7 bit 7 only applies to COS (“C”) boards Read Base + 0 (+1, +2, +4, +5, +6) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 D7 of input data D6 of input data D5 of input data D4 of input data D3 of input data D2 of input data D1 of input data D0 of input data Reading a byte from the Port Data Base Address reads the 8 bits associated with that half of a port. The Addresses labeled “Low Byte” are associated with pins 1 through 25, and the Addresses labeled “High Byte” are associated with pin 26 through 50, as shown in Chapter 6, connector pin assignments. Writing to these addresses has no effect. Address Base +7 is used to control and monitor Change-of-State IRQs. To enable COS IRQs, write a “1" to bit 7; disable by writing “0" to bit 7. This enable status can be read back; that is, a read from Base +7 will show bit 7 High (“1") while COS IRQs are enabled. While COS IRQs are enabled, any change of input level (low-to-high or high-to-low) on any of the 48 bits will cause an IRQ to be generated. After an IRQ is generated, bit 6 of Base +7 will be set Low (“0"), which can be used to confirm that a shared interrupt was generated by this card. Any read of Base +7 will clear the IRQ latch and return bit 6 to its High (“1") state. Please note: Enabling or Disabling IRQs does not clear the IRQ latch. If you disable IRQs while one is pending, it is still required to read from Base +7 to clear the pending IRQ. Read Base + 7: COS Status Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 IRQ Enable Status IRQ Status (Active Low) N/A N/A N/A N/A N/A N/A Write Base + 7: COS Enable/Disable Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 IRQ Enable/ Disable N/A N/A N/A N/A N/A N/A N/A Chapter 6: Connector Pin Assignments Isolated inputs are connected to the card via a 50-pin HEADER type connector. There are three connectors named PORT0, PORT1, and PORT2. The table below ...