Stimmen - 3, Durchschnittliche Bewertung: 3.3
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Anleitung Zusammenfassung
769 512 Core Reset Control Bit Locations .............................................................................. 773 513 Internal Bus Reset Control Bit Locations.................................................................... 775 514 Internal Bus Reset Summary ................................................................................... 775 515 Reset Pin Summary................................................................................................ 777 516 TPER Mode Per Function Storage Port Allocation (CONTROLLER_ONLY#=1) ................ 778 517 Non-TPER Mode Per Function Storage Port Allocation (CONTROLLER_ONLY#=0) ......... 778 518 Reset Strap Signals ................................................................................................ 780 519 TLU TAP Controller Instruction Set............................................................................ 791 520 IOP Device ID Register Field Definitions ................................................................... 792 521 IOP Device ID Register Settings ............................................................................... 792 522 PMMR Base Address Register (PMMRBAR) Default Value .............................................. 798 523 Local Addresses for Integrated Peripherals ................................................................ 798 524 PBI Base Address Offset.......................................................................................... 801 525 Peripheral Bus Interface Unit ................................................................................... 801 526 SC Base Address Offset........................................................................................... 802 527 System Controller Unit............................................................................................ 802 528 Internal Bus Bridge Base Address Offset.................................................................... 802 529 Internal Bus Bridge ................................................................................................ 802 530 I/O Pad Control Base Address Offset......................................................................... 803 531 I/O Pad Control Unit............................................................................................... 803 532 UART 0-1 Offset..................................................................................................... 804 533 UART.................................................................................................................... 804 534 GPIO Offset........................................................................................................... 805 535 GPIO .................................................................................................................... 805 2 536 I C 0-2 Offset........................................................................................................ 805 537 I2C Unit................................................................................................................ 805 538 Messaging Unit Offset............................................................................................. 806 539 Messaging Unit ...................................................................................................... 806 540 PMON Unit Base Address Offset. ............................................................................. 808 541 PMON Unit ........................................................................................................... 808 542 PCI Function MMR Locations .................................................................................... 809 ® 543 Intel 413808 and 413812 I/O Controllers ATUX Configuration Space Base Address Offset ... 810 544 Address Translation Unit Registers — ATUX ............................................................... 811 ® Intel 413808 and 413812 I/O Controllers in TPER Mode October 2007 Developer’s Manual Order Number: 317805-001US Intel ® 413808 and 413812—Contents ® 545 Intel 413808 and 413812 I/O Controllers ATUE Configuration Space Base Address Offset... 814 546 Address Translation Unit Registers — ATUE ................................................................815 ® 547 Intel 413808 and 413812 I/O Controllers in TPER Mode PCI Function Visibility..............819 548 Coprocessor Registers Assigned to Integrated Peripherals ............................................819 549 Coprocessor Register Locations ................................................................................820 ® Intel 413808 and 413812 I/O Controllers in TPER Mode Developer’s Manual October 2007 Order Number: 317805-001US Contents—Intel ® 413808 and 413812 Revision History Date Revision Description October 2007 001 Initial Release. ® Intel 413808 and 413812 I/O Controllers in TPER Mode October 2007 Developer’s Manual Order Number: 317805-001US Intel ® 413808 and 413812—Introduction...