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Anleitung Zusammenfassung
The embedded nonvolatile elements incorporate QuantumTrap™ technology producing the world’s most reliable nonvolatile memory. The SRAM provides unlimited read and write cycles, while independent, nonvolatile data resides in the highly reliable QuantumTrap cell. Data transfers from the SRAM to the nonvolatile elements (the STORE operation) takes place automatically at power down. On power up, data is restored to the SRAM (the RECALL operation) from the nonvolatile memory. Both the STORE and RECALL operations are also available under software control. Logic Block Diagram Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Document Number: 001-50595 Rev. ** Revised January 29, 2009 [+] Feedback STK16C88 ...................................... Pin Configurations Figure 1. Pin Diagram - 28-Pin PDIP .... .... .. .. .. .. .. .. .. .. .... .... .... ....6 .. .. .. .. .. .... ........ .. .. .. .. .. .. .. .. ....& ..( .... .. .. .... ..( .... ..( .... .... .... .... .... Table 1. Pin Definitions - 28-Pin PDIP Pin Name Alt IO Type Description A0–A14 Input Address Inputs. Used to select one of the 32,768 bytes of the nvSRAM. DQ0-DQ7 Input or Output Bidirectional Data IO lines. Used as input or output lines depending on operation. WE W Input Write Enable Input, Active LOW. When the chip is enabled and WE is LOW, data on the IO pins is written to the specific address location. CE E Input Chip Enable Input, Active LOW. When LOW, selects the chip. When HIGH, deselects the chip. OE G Input Output Enable, Active LOW. The active LOW OE input enables the data output buffers during read cycles. Deasserting OE HIGH causes the IO pins to tri-state. VSS Ground Ground for the Device. The device is connected to ground of the system. VCC Power Supply Power Supply Inputs to the Device. Document Number: 001-50595 Rev. ** Page 2 of 14 [+] Feedback STK16C88 Device Operation The AutoStore+ STK16C88 is a fast 32K x 8 SRAM that does not lose its data on power down. The data is preserved in integral QuantumTrap nonvolatile storage elements when power is lost. Automatic STORE on power down and automatic RECALL on power up guarantee data integrity without the use of batteries. SRAM Read The STK16C88 performs a READ cycle whenever CE and OE are LOW while WE is HIGH. The address specified on pins A0–14 determines the 32,768 data bytes accessed. When the READ is initiated by an address transition, the outputs are valid after a delay of tAA (READ cycle 1). If the READ is initiated by CE or OE, the outputs are valid at tACE or at tDOE, whichever is later (READ cycle 2). The data outputs repeatedly respond to address changes within the tAA access time without the need for transitions on any control input pins, and remains valid until another address change or until CE or OE is brought HIGH. SRAM Write A WRITE cycle is performed whenever CE and WE are LOW. The address inputs must be stable prior to entering the WRITE cycle and must remain stable until either CE or WE goes HIGH at the end of the cycle. The data on the common IO pins DQ0–7 are written into the memory if it has valid tSD, before the end of a WE controlled WRITE or before the end of an CE controlled WRITE. Keep OE HIGH during the entire WRITE cycle to avoid data bus contention on common IO lines. If OE is left LOW, internal circuitry turns off the output buffers tHZWE after WE goes LOW. AutoStore+ Operation The STK16C88’s automatic STORE on power down is completely transparent to the system. The STORE initiation takes less than 500 ns when power is lost (VCC < VSWITCH) at which point the part depends only on its internal capacitor for STORE completion. If the power supply drops faster than 20 .s/volt before Vcc reaches Vswitch, then a 2.2 ohm resistor should be inserted between Vcc and the system supply to avoid a momentary excess of current between Vcc and internal capacitor. In order to prevent unneeded STORE operations, automatic STOREs are ignored unless at least one WRITE operation has taken place since the most recent STORE or RECALL cycle. Software initiated STORE cycles are performed regardless of whether or not a WRITE operation has taken place. Hardware RECALL (Power Up) During power up or after any low power condition (VCC