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4-20 C141-E050-02EN 4.7 Servo Control d) During phase switching, the spindle motor starts rotating in low speed, and generates a counter electromotive force. The SVC detects this counter electromotive force and reports to the MPU using a PHASE signal for speed detection. e) The MPU is waiting for a PHASE signal. When no phase signal is sent for a sepcific period, the MPU resets the SVC and starts from the beginning. When a PHASE signal is sent, the SVC enters the acceleration mode. (2) Acceleration mode In this mode, the MPU stops to send the phase switching signal to the SVC. The SVC starts a phase switching by itself based on the counter electromotive force. Then, rotation of the spindle motor accelerates. The MPU calcurates a rotational speed of the spindle motor based on the PHASE signal from the SVC, and accelerates till the rotational speed reaches 4,000 rpm. When the rotational speed reaches 4,000 rpm, the SVC enters the stable rotation mode. (3) Stable rotation mode The MPU calcurates a time for one revolution of the spindle motor based on the PHASE signal from the SVC. The MPU takes a difference between the current time and a time for one revolution at 4,000 rpm that the MPU already recognized. Then, the MPU keeps the rotational speed to 4,000 rpm by charging or discharging the charge pump for the different time. For example, when the actual rotational speed is 3,800 rpm, the time for one revolution is 15.789 ms. And, the time for one revolution at 4,000 rpm is 15 ms. Therefore, the MPU charges the charge pump for 0.789 ms . k (k: constant value). This makes the flowed current into the motor higher and the rotational speed up. When the actual rotational speed is faster than 4,000 rpm, the MPU discharges the pump the other way. This control (charging/discharging) is performed every 1 revolution. C141-E050-02EN 4-21 CHAPTER 5 Interface 5.1 Physical Interface 5.2 Logical Interface 5.3 Host Commands 5.4 Command Protocol 5.5 Ultra DMA Feature Set 5.6 Timing This chapter gives details about the interface, and the interface commands and timings. C141-E050-02EN Interface 5.1 Physical Interface 5.1.1 Interface signals Figure 5.1 shows the interface signals. INTRQ: INTERRUPT REQUEST IOCS16-: 16-BIT I/O PDIAG: PASSED DIAGNOSTICS DASP-: DEVICE ACTIVE/SLAVE PRESENT DIOW-: I/O WRITE STOP: STOP DURING ULTRA DMA DATA BURSTS DIOR-: I/O READ HDMARDY: DMA READY DURING ULTRA DMA DATA IN BURSTS HSTROBE: DATA STROBE DURING ULTRA DMA DATA OUT BURSTS IORDY: I/O READY DDMARDY: DMA READY DURING ULTRA DMA DATA OUT BURSTS DSTROBE: DATA STROBE DURING ULTRA DMA DATA IN BURSTS Figure 5.1 Interface signals C141-E050-02EN 5.1 Physical Interface 5.1.2 Signal assignment on the connector Table 5.1 shows the signal assignment on the interface connector. Table 5.1 Signal assignment on the interface connector Pin No. Signal Pin No. Signal A ENCSEL B GND C ENCSEL D MSTR E (KEY) F (KEY) 1 RESET– 2 GND 3 DATA7 4 DATA8 5 DATA6 6 DATA9 7 DATA5 8 DATA10 9 DATA4 10 DATA11 11 DATA3 12 DATA12 13 DATA2 14 DATA13 15 DATA1 16 DATA14 17 DATA0 18 DATA15 19 GND 20 (KEY) 21 DMARQ 22 GND 23 DIOW-, STOP 24 GND 25 DIOR-, HDMRDY, HSTROBE 26 GND 27 IORDY, DDMARDY, DSTROBE 28 CSEL 29 DMACK– 30 GND 31 INTRQ 32 IOCS16– 33 DA1 34 PDIAG 35 DA0 36 DA2 37 CS0– 38 CS1– 39 DASP– 40 GND 41 +5 VDC 42 +5 VDC 43 GND 44 unused C141-E050-02EN Interface [signal] [I/O] [Description] ENCSEL I This signal is used to set master/slave using the CSEL signal (pin 28). Pins A and C Open: Sets master/slave by the MSTR signal without using the CSEL signal. Short: Sets master/slave using the CSEL signal. The MSTR signal is ignored. MSTR I MSTR, I, Master/slave setting 1: Master 0: Slave RESET-I Reset signal from the host. This signal is low active and is asserted for a minimum of 25 ms during power on. DATA 0-15 I/O Sixteen-bit bi-directional data bus between the host and the device. These signals are used for data transfer DIOW-I Signal asserted by the host to write to the device register or data port. STOP I DIOW- must be negated by the host before starting the Ultra DMA transfer. The STOP signal must be negated by the host before data is transferred during the Ultra DMA transfer. During data transfer in Ultra DMA mode, the assertion of the STOP signal asserted by the host later indicates that the transfer has been suspended. DIOR-I Read strobe signal from the host to read the device register or data port HDMARDY-I Flow control signal for Ultra DMA data In transfer (READ DMA command). This signal is asserted by the host to inform the device that the host is ready to receive the Ultra DMA data In transfer. The host can negate the HDMARDY- signal to suspend the Ultra DMA data In transfer. HSTROBE I Data Out Strobe signal from the host during Ultra DMA data Out transfer (WRITE DMA command). Both the rising and falling edges of the HSTROBE signal latch data from Data 15-0 into the device. The host can suspend the inversion of the HSTROBE signal to suspend the Ultra DMA data Out transfe...

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